? semiconductor components industries, llc, 2001 april, 2001 rev. 0 1 publication order number: mjb44h11/d mjb44h11 (npn), mjb45h11 (pnp) preferred devices complementary power transistors d 2 pak for surface mount . . . for general purpose power amplification and switching such as output or driver stages in applications such as switching regulators, converters and power amplifiers. ? low collectoremitter saturation voltage v ce(sat) = 1.0 v (max) @ 8.0 a ? fast switching speeds ? complementary pairs simplifies designs maximum ratings rating symbol value unit ???????????? ???????????? collectoremitter voltage ???? ???? v ceo ??? ??? 80 ??? ??? vdc ???????????? ???????????? emitterbase voltage ???? ???? v eb ??? ??? 5 ??? ??? vdc ???????????? ? ?????????? ? ???????????? collector current continuous peak ???? ? ?? ? ???? i c ??? ? ? ? ??? 10 20 ??? ? ? ? ??? adc ???????????? ? ?????????? ? ???????????? total power dissipation @ t c = 25 c derate above 25 c ???? ? ?? ? ???? p d ??? ? ? ? ??? 50 1.67 ??? ? ? ? ??? watts w/ c ???????????? ? ?????????? ? ? ?????????? ? ???????????? total power dissipation @ t a = 25 c derate above 25 c ???? ? ?? ? ? ?? ? ???? p d ??? ? ? ? ? ? ? ??? 2.0 0.016 ??? ? ? ? ? ? ? ??? watts w/ c ???????????? ? ?????????? ? ???????????? operating and storage junction temperature range ???? ? ?? ? ???? t j , t stg ??? ? ? ? ??? 55 to 150 ??? ? ? ? ??? c ??????????????????? ??????????????????? thermal characteristics ???????????? ???????????? characteristic ???? ???? symbol ??? ??? max ??? ??? unit ???????????? ???????????? thermal resistance, junction to case ???? ???? r q jc ??? ??? 2.5 ??? ??? c/w ???????????? ???????????? thermal resistance, junction to ambient ???? ???? r q ja ??? ??? 75 ??? ??? c/w device package shipping ordering information mjb44h11 d 2 pak http://onsemi.com d 2 pak case 418b style 1 50 units/rail preferred devices are recommended choices for future use and best overall value. marking diagram yww mjb 4xh11 silicon power transistors 10 amperes 80 volts 50 watts y = year ww = work week mjb4xh11 = specific device code x = 4 or 5 mjb44h11t4 d 2 pak 800/tape & reel mjb45h11 d 2 pak 50 units/rail mjb45h11t4 d 2 pak 800/tape & reel
mjb44h11 (npn), mjb45h11 (pnp) http://onsemi.com 2 ????????????????????????????????? ????????????????????????????????? electrical characteristics (t c = 25 c unless otherwise noted) ??????????????????? ??????????????????? characteristic ????? ????? symbol ??? ??? min ???? ???? typ ???? ???? max ??? ??? unit ????????????????????????????????? ????????????????????????????????? off characteristics ??????????????????? ? ????????????????? ? ??????????????????? collectoremitter sustaining voltage (i c = 30 ma, i b = 0) ????? ? ??? ? ????? v ceo(sus) ??? ? ? ? ??? 80 ???? ? ?? ? ???? ???? ? ?? ? ???? ??? ? ? ? ??? vdc ??????????????????? ? ????????????????? ? ??????????????????? collector cutoff current (v ce = rated v ceo , v be = 0) ????? ? ??? ? ????? i ces ??? ? ? ? ??? ???? ? ?? ? ???? ???? ? ?? ? ???? 10 ??? ? ? ? ??? m a ??????????????????? ? ????????????????? ? ??????????????????? emitter cutoff current (v eb = 5 vdc) ????? ? ??? ? ????? i ebo ??? ? ? ? ??? ???? ? ?? ? ???? ???? ? ?? ? ???? 50 ??? ? ? ? ??? m a ????????????????????????????????? ????????????????????????????????? on characteristics ??????????????????? ??????????????????? collectoremitter saturation voltage (i c = 8 adc, i b = 0.4 adc) ????? ????? v ce(sat) ??? ??? ???? ???? ???? ???? 1.0 ??? ??? vdc ??????????????????? ? ????????????????? ? ??????????????????? baseemitter saturation voltage (i c = 8 adc, i b = 0.8 adc) ????? ? ??? ? ????? v be(sat) ??? ? ? ? ??? ???? ? ?? ? ???? ???? ? ?? ? ???? 1.5 ??? ? ? ? ??? vdc ??????????????????? ? ????????????????? ? ??????????????????? dc current gain (v ce = 1 vdc, i c = 2 adc) ????? ? ??? ? ????? h fe ??? ? ? ? ??? 60 ???? ? ?? ? ???? ???? ? ?? ? ???? ??? ? ? ? ??? ??????????????????? ? ????????????????? ? ??????????????????? dc current gain (v ce = 1 vdc, i c = 4 adc) ????? ? ??? ? ????? ??? ? ? ? ??? 40 ???? ? ?? ? ???? ???? ? ?? ? ???? ??? ? ? ? ??? ????????????????????????????????? ????????????????????????????????? dynamic characteristics ??????????????????? ? ????????????????? ? ??????????????????? collector capacitance (v cb = 10 vdc, f test = 1 mhz) mjb44h11 mjb45h11 ????? ? ??? ? ????? c cb ??? ? ? ? ??? ???? ? ?? ? ???? 130 230 ???? ? ?? ? ???? ??? ? ? ? ??? pf ??????????????????? ? ????????????????? ? ? ????????????????? ? ??????????????????? gain bandwidth product (i c = 0.5 adc, v ce = 10 vdc, f = 20 mhz) mjb44h11 mjb45h11 ????? ? ??? ? ? ??? ? ????? f t ??? ? ? ? ? ? ? ??? ???? ? ?? ? ? ?? ? ???? 50 40 ???? ? ?? ? ? ?? ? ???? ??? ? ? ? ? ? ? ??? mhz ??????????????????? ??????????????????? switching times ????? ????? ??? ??? ???? ???? ???? ???? ??? ??? ??????????????????? ? ????????????????? ? ??????????????????? delay and rise times (i c = 5 adc, i b1 = 0.5 adc) mjb44h11 mjb45h11 ????? ? ??? ? ????? t d + t r ??? ? ? ? ??? ???? ? ?? ? ???? 300 135 ???? ? ?? ? ???? ??? ? ? ? ??? ns ??????????????????? ? ????????????????? ? ? ????????????????? ? ??????????????????? storage time (i c = 5 adc, i b1 = i b2 = 0.5 adc) mjb44h11 mjb45h11 ????? ? ??? ? ? ??? ? ????? t s ??? ? ? ? ? ? ? ??? ???? ? ?? ? ? ?? ? ???? 500 500 ???? ? ?? ? ? ?? ? ???? ??? ? ? ? ? ? ? ??? ns ??????????????????? ? ????????????????? ? ??????????????????? fall time (i c = 5 adc, i b1 = i b2 = 0.5 adc) mjb44h11 mjb45h11 ????? ? ??? ? ????? t f ??? ? ? ? ??? ???? ? ?? ? ???? 140 100 ???? ? ?? ? ???? ??? ? ? ? ??? ns
mjb44h11 (npn), mjb45h11 (pnp) http://onsemi.com 3 figure 1. thermal response t, time (ms) 0.01 0.01 0.05 1.0 2.0 5.0 10 20 50 500 1.0 k 0.1 0.5 0.2 1.0 0.2 0.1 0.05 r(t), transient thermal z q jc(t) = r(t) r q jc r q jc = 1.56 c/w max d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) z q jc(t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 0.2 single pulse resistance (normalized) 0.5 d = 0.5 0.05 0.3 0.7 0.07 0.03 0.02 0.02 100 200 0.1 0.02 0.01 figure 2. maximum rated forward bias safe operating area 100 1.0 v ce , collector-emitter voltage (volts) 5.0 10 t c 70 c duty cycle 50% i c , collector current (amps) 2.0 3.0 20 30 50 100 1.0 7.0 70 1.0 m s dc 0.1 0.2 0.3 0.5 2.0 3.0 5.0 10 20 30 50 10 m s 100 m s 1.0 ms there are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. safe operating area curves indicate i c v ce limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate. the data of figure 2 is based on t j(pk) = 150 c; t c is variable depending on conditions. second breakdown pulse limits are valid for duty cycles to 10% provided t j(pk) 150 c. t j(pk) may be calculated from the data in figure 1. at high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. figure 3. power derating 0 t, temperature ( c) 0 40 60 100 120 160 40 t c 20 60 p d , power dissipation (watts) 0 2.0 t a 1.0 3.0 80 140 t c t a 20
mjb44h11 (npn), mjb45h11 (pnp) http://onsemi.com 4 i c , collector current (amps) i c , collector current (amps) i c , collector current (amps) h fe , dc current gain v ce = 4 v t j = 125 c 25 c -40 c 1000 0.1 figure 4. mjb44h11 dc current gain 10 110 100 figure 5. mjb45h11 dc current gain figure 6. mjb44h11 current gain versus temperature figure 7. mjb45h11 current gain versus temperature i c /i b = 10 t j = 25 c 0.1 figure 8. mjb44h11 onvoltages i c , collector current (amps) 1 0.8 saturation voltage (volts) 1.2 0.4 0 0.6 0.2 110 t j = 25 c figure 9. mjb45h11 onvoltages v ce = 1 v i c /i b = 10 t j = 25 c 0.1 i c , collector current (amps) 1 0.8 saturation voltage (volts) 1.2 0.4 0 0.6 0.2 110 h fe , dc current gain 1000 0.1 10 110 100 v ce = 1 v i c , collector current (amps) h fe , dc current gain v ce = 4 v 1000 0.1 10 110 100 t j = 25 c 1 v t j = 125 c 25 c -40 c h fe , dc current gain 1000 0.1 10 110 100 v ce = 1 v v be(sat) v ce(sat) v be(sat) v ce(sat)
mjb44h11 (npn), mjb45h11 (pnp) http://onsemi.com 5 information for using the d 2 pak surface mount package recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. with the correct pad geometry, the packages will self align when subjected to a solder reflow process. mm inches 0.33 8.38 0.08 2.032 0.04 1.016 0.63 17.02 0.42 10.66 0.12 3.05 0.24 6.096 power dissipation for a surface mount device the power dissipation for a surface mount device is a function of the collector pad size. these can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. power dissipation for a surface mount device is determined by t j(max) , the maximum rated junction temperature of the die, r q ja , the thermal resistance from the device junction to ambient, and the operating temperature, t a . using the values provided on the data sheet, p d can be calculated as follows: p d = t j(max) t a r q ja the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device. for a d 2 pak device, p d is calculated as follows. p d = 150 c 25 c 50 c/w = 2.5 watts the 50 c/w for the d 2 pak package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 w atts. there are other alternatives to achieving higher power dissipation from the surface mount packages. one is to increase the area of the collector pad. by increasing the area of the collection pad, the power dissipation can be increased. although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. for example, a graph of r q ja versus collector pad area is shown in figure 10. figure 10. thermal resistance versus collector pad area for the d 2 pak package (typical) 2.5 watts a, area (square inches) board material = 0.0625 g-10/fr-4, 2 oz copper t a = 25 c r , thermal resistance, junctionto ambient (c/w) q ja 60 70 50 40 30 20 16 14 12 10 8 6 4 2 0 3.5 watts 5 watts another alternative would be to use a ceramic substrate or an aluminum core board such as thermal clad ? . using a board material such as thermal clad, an aluminum core board, the power dissipation can be doubled using the same footprint.
mjb44h11 (npn), mjb45h11 (pnp) http://onsemi.com 6 solder stencil guidelines prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. solder stencils are used to screen the optimum amount. these stencils are typically 0.008 inches thick and may be made of brass or stainless steel. for packages such as the sc59, sc70/sot323, sod123, sot23, sot143, sot223, so8, so14, so16, and smb/smc diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. this is not the case with the dpak and d 2 pak packages. if one uses a 1:1 opening to screen solder onto the collector pad, misalignment and/or atombstoningo may occur due to an excess of solder. for these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. the opening for the leads is still a 1:1 registration. figure 11. shows a typical stencil for the dpak and d 2 pak packages. the pattern of the opening in the stencil for the collector pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. ?? ?? ?? ?? ?? ??? ??? ??? ??? ??? ??? ??? ??? ?? ?? figure 11. typical stencil for dpak and d 2 pak packages solder paste openings stencil soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling. * soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * due to shadowing and the inability to set the wave height to incorporate other surface mount components, the d 2 pak is not recommended for wave soldering.
mjb44h11 (npn), mjb45h11 (pnp) http://onsemi.com 7 typical solder heating profile for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones, and a figure for belt speed. taken together, these control settings make up a heating aprofileo for that particular circuit board. on machines controlled by a computer, the computer remembers these profiles from one operating session to the next. figure 12. shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows temperature versus time. the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/infrared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. step 1 preheat zone 1 ramp" step 2 vent soak" step 3 heating zones 2 & 5 ramp" step 4 heating zones 3 & 6 soak" step 5 heating zones 4 & 7 spike" step 6 vent step 7 cooling 200 c 150 c 100 c 50 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies 100 c 150 c 160 c 170 c 140 c desired curve for high mass assemblies figure 12. typical solder heating profile
mjb44h11 (npn), mjb45h11 (pnp) http://onsemi.com 8 package dimensions d 2 pak case 418b03 issue d notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. style 1: pin 1. base 2. collector 3. emitter 4. collector seating plane s g d t m 0.13 (0.005) t 23 1 4 3 pl k j h v e c a dim min max min max millimeters inches a 0.340 0.380 8.64 9.65 b 0.380 0.405 9.65 10.29 c 0.160 0.190 4.06 4.83 d 0.020 0.035 0.51 0.89 e 0.045 0.055 1.14 1.40 g 0.100 bsc 2.54 bsc h 0.080 0.110 2.03 2.79 j 0.018 0.025 0.46 0.64 k 0.090 0.110 2.29 2.79 s 0.575 0.625 14.60 15.88 v 0.045 0.055 1.14 1.40 b m b on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 13036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mjb44h11/d thermal clad is a registered trademark of the bergquist company north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland
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